Question: 2 . Calculate the maximum frequency of the input clock in the Clock divider below. The delay of the inverter is 3 0 0 ps

2. Calculate the maximum frequency of the input clock in the Clock divider below. The delay of the inverter is 300 ps each, and the CLK-to-Q delay of the Flip-flop is 50 ps . The setup/hold time for both is 50 ps . Disregard jitter. (15pts)
Figure. Clock divider
2 . Calculate the maximum frequency of the input

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