$2.$ Design a sequential circuit that has a primary input $\backslash ($ w $\backslash )$ and a final output $\backslash ($ z $\backslash ).$ Each clock cycle, the primary input $\backslash ($ w $\backslash ),$ receives a high pulse $($i$.$e$.1),$ or a low pulse $($i$.$e$.0).$ When a sequence of three consecutive pulses $\text{'}101\text{'}$ are received at the primary input in three consecutive clock cycles then the final output $($z$)$ of this sequential circuit is to produce an output $\backslash ($ z$=1\backslash ),$ to indicate the successful detection of input signal $\text{'}101\text{'}$ in three consecutive cycles.

Utilizing the concept of FSM $($Finite State Machine$)$ derive State Diagram, State Table, State Assigned Table for the sequential circuit that produces output z$=1$ when it detects an overlapping sequence of $\backslash ($ w$=101\backslash ),$ otherwise $\backslash ($ z$=0\backslash ).$

Also, note for design of this Sequential circuit, you should use at least one JK flip$-$flop and at least one T flip$-$flop.