$2-$ Design and Simulation of Sequential Components in Altera Quartus using VHDL

$2\mathrm{.}1-$ Data Flip Flop $($DFF$)$

$2\mathrm{.}2-1-$Bit Register

$2\mathrm{.}3-16-$Bit Register

$2\mathrm{.}4-$ Program Counter Register

$2\mathrm{.}5-8$ Register RAM

Then with that code generate a timing diagram $(.$vwf file$)$