2. In this question, we examine how data dependencies affect execution in the basic 5-stage pipeline described in the lectures (Section 4.5 in the text book). Problems in this exercise refer to the following sequence of instructions or r1, r2, r3 or r2, rl, r4 or r1, ri, r2 Also, assume the following cycle times shown in Table 3 for each of the options related to forwarding: Without Forwarding | With Full Forwarding|With ALU-ALU Forwarding Only 250ps 300ps 290ps Table 3: Cycle Times for different options (a) Indicate dependencies and their type (b) Assume there is no forwarding in this pipelined processor, indicate hazards and add nop struction to eliminate them (c) Assume there is full forwarding. Indicate hazards and add NOP instruction to eliminate them (d) What is the total execution time of this instruction sequence without forwarding and with full forwarding? What is the speedup achieved by adding full forwarding to a pipeline that had no forwarding? (no forwarding from the MEM to the EX stage) What is the speedup over a no-forwarding pipeline? (e) Add nop instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (f) What is the total execution time of this instruction sequence with only ALU-ALU forwarding