Question: 2. Suppose the latencies in various logic circuits, both for reading and writing, needed to implement the single-cycle datapath are as shown below. PC

2. Suppose the latencies in various logic circuits, both for reading and

2. Suppose the latencies in various logic circuits, both for reading and writing, needed to implement the single-cycle datapath are as shown below. PC I-Mem Regs ALU Adder Mux Sign-Ext Shift-Left 50ps 200ps 80ps 90ps 70ps 20ps 15ps 10ps How long will it take to execute the following instructions in a single-cycle MIPS implementation shown on the next page. (a) lw instruction (b) sw instruction D-Mem 250ps (c) sub instruction

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