Question: The processor in Q1 above is converted into a 10-stage pipeline. The slowest of these 10 stages takes 250 ps (including latch overheads). What is

The processor in Q1 above is converted into a 10-stage pipeline. The slowest of these 10 stages takes 250 ps (including latch overheads).

What is the clock speed of this processor? (5 points)

What is the CPI of this processor, assuming that every load/store instruction finds its instruction/data in the instruction or data cache, and there are no stalls from data/control/structural hazards? (5 points)

What is the throughput of this processor (in billion instructions per second)? (10 points)

What is the speedup, relative to the unpipelined processor in Q1? Why is the speedup less than 10X? (10 points)

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