2. (Total 30 points) Consider the counter with parallel-load capability in Fig. 5.24 in textbook. For the D flip-flops, assume that the setup time ts,, is 4 ns, the hold time t is 4 ns, and the clock-to-Q propagation delay too is 3 to 4 ns. Assume that the propagation delays for AND gates, XOR gates and 2-to-1 multiplexers are 3 ns, 3 ns and 5 ns, respectively. (a) (20 points) What is the maximum clock frequency for which the circuit will operate correctly? Please show your calculations. (b) (10 points) Does the circuit have hold time violation? Briefly, explain your answer.