25.A new instruction, SMR (Store Multiple Registers), with symbolic opcode name SMR, is to be implemented for the multiple-cycle computer. The instruction stores the contents of eight registers in eight consecutive memory locations. Register R[SA] species the address in memory M to which the rst register R[SB] is to be stored. The registers to be stored are R[SB], R [(SB + 1) modulo 8], ..., R [(SB + 7) modulo 8] in Memory M Addresses R[SA], R[SA] + 1, ..., R[SA] + 7. Design this instruction presenting your nal results in the form shown in Table 15.

26.A new instruction LMR (Load Multiple Registers), with symbolic opcode name LMR, is to be implemented for the multiple-cycle computer. The instruction is to retrieve the register contents stored by use of SMR in Problem 25 from memory M and place it in the eight registers. Assume that R[SA] and SB have same values as for SMR for such a retrieval. Design this instruction presenting your nal results in the form shown in Table 15. this questions from logic and computer design fundamentals book edition 4