Question: 3. Assume a 64B direct-mapped cache whose block size is 16B. The memory is 256B. In addition, assume that the system has been running for

3. Assume a 64B direct-mapped cache whose block size is 16B. The memory is 256B. In addition, assume that the system has been running for a while and there are no more compulsory misses (i.e., all of the data from memory was at least once in the cache). Assume that the 4 blocks in the cache include data from addresses 13, 57, 216 and 233. a. Write a sequence of address accesses such that the sequence contains only conflict misses (i.e., no hits and no capacity misses). b. Write a sequence of address accesses such that the sequence contains only capacity misses (i.e., no hits and no conflict misses). C. Can the performance improve for the sequences you wrote above if we were to use a fully associative cache with perfect replacement policy? Explain. d. Assuming that the 64B cache is now fully associative and its block size is as before (16B). Come up with a periodic sequence of addresses, such that utilization of perfect replacement policy is degrading the performance of the system compared with a less fancy replacement policy (e.... random replacement policy)

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