(3) Assume a five-stage single-pipeline microarchitecture (fetch, decode, execute, memory, write-back) and the following code. Loop:...

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(3) Assume a five-stage single-pipeline microarchitecture (fetch, decode, execute, memory, write-back) and the following code. Loop: 1 LW R3, 0(RO); 2 LW R1, 0(R3); 345 ADDI R1, R1, #1; SUB R4, R3, R2; SW R1, 0(R3); 6 BNEZ R4, Loop; Deliverables: Please draw the waterfall diagram like the following first, and use that to write a short answer (i.e., a few sentences) to each of the questions. ( instruction, cycle ) 1 2 3 1 IF ID EX 456789112345648037 WMW .' W B 22 2 O OO 3 4 5 6 7 IF ID MEM EX W W B Please add more rows or columns as needed. Please shrink the font as needed. Here, we use "O" to represent pipeline bubbles caused by hazards, and "--" to represent the extra cycles for LW and SW. (3) Assume a five-stage single-pipeline microarchitecture (fetch, decode, execute, memory, write-back) and the following code. Loop: 1 LW R3, 0(RO); 2 LW R1, 0(R3); 345 ADDI R1, R1, #1; SUB R4, R3, R2; SW R1, 0(R3); 6 BNEZ R4, Loop; Deliverables: Please draw the waterfall diagram like the following first, and use that to write a short answer (i.e., a few sentences) to each of the questions. ( instruction, cycle ) 1 2 3 1 IF ID EX 456789112345648037 WMW .' W B 22 2 O OO 3 4 5 6 7 IF ID MEM EX W W B Please add more rows or columns as needed. Please shrink the font as needed. Here, we use "O" to represent pipeline bubbles caused by hazards, and "--" to represent the extra cycles for LW and SW.