$3.$ Find the overall worst$-$case delay $($e$.$ the delay at which all the outputs of the circuit are finalized$)$ for each of the unsigned adder circuits mentioned below $($carry$-$in to the first bit position$=0$ in each case$).$ Assume that the delay due to one level of gates is D$.$ Also, assume that inverted versions of signal variables are already available $($i$.$e$.$ ignore inverter delays$).$ Furthermore, assume unlimited fan$-$in unless specified otherwise.

$1.16-$bit block CLA $($BCLA$)$ with block size$=8$

$2.16-$bit block CLA $($BCLA$)$ with block size$=4$

$3.16-$bit block RCA$-$BCL adder with block size $\backslash (=8\backslash )$

$4.16-$bit block RCA$-$BCL adder with block size$=4$

$5.16-$bit block carry$-$skip adder $($CSA$)$ with block size$=2$

$6.16-$bit block carry$-$select adder $($CSeIA$)$ with block size$=4.$ Assume that the first block is implemented as an RCA