$3.$ If we change load$/$store instructions to use a register $($without an offset$)$ as the address, these$$ instructions no longer need to use the ALU. $($See Problem $4$ in HW $4)$ As a result, the MEM and EX stages can be overlapped and the pipeline has only four stages.$$

$3\mathrm{.}1$ How will the reduction in pipeline depth affect the cycle time?$$

$3\mathrm{.}2$ How might this change improve the performance of the pipeline?$$

$3\mathrm{.}3$ How might this change degrade the performance of the pipeline?