3. Problem 5.10 from textbook 5.10 In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The following table shows data for L1 caches attached to each of two processors, P1 and P2 LI Size 2 K?IS 4 KiB LI Miss Rate PI P2 LI Hit Time 0.66ns 0.90ns 60% 5.10. 1 [5] Assuming that the LI hit time determines the cycle times for P1 and P2, what are their respective clock rates? 5.10.2 [101 What is the Average Memory Access Time for Pl and P2 (in cycles)? 5.10.3 [5]