Question 3: For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache Tag Index Offset 31-10 9-5 40 a. What is the cache block size (in words)? b. How many entries does the cache have? c. What is the ratio between total bits required for such a cache implementation over the data storage bits? Question 4: In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. The following table shows data for L1 caches attached to each of two processors, Pl and P2. L1 Size Li Miss Rate Li Hit Time P1 2 KB 8.0% 0.66 ns P2 4 KB 6.0% 0.90 ns a. Assuming that the LI hit time determines the cycle times for Pl and P2, what are their respective clock rates? b. What is the Average Memory Access Time for Pl and P2? C. Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster