$3.$ Read the following Verilog code and find out what it does. State your reasoning.

$```$

module ques$4($w$,$y$)$;

input $[3$:$0]$w;

output reg $[1$:$0]$y;

always@$($w$)$

begin

casex $($w$)$

$\text{'}$b$1000$:y$=3$;

$\text{'}$bx$100$:y$=2$;

$\text{'}$bxx$10$:y$=1$;

default:y$=0$;

endcase

end

endmodule

$```$