3. Write the equivalent structural verilog code for the behavioral verilog code below that does a...

 

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3. Write the equivalent structural verilog code for the behavioral verilog code below that does a y=x function. input [2:0] x; output [6:0] y; reg [6:0] y; wire [2:0] x; always @(x) begin y=0; case(x) 3'b000: y=0; 3'b001: y=1; 3'b010: y=8; 3'b011: y=27; end 3'b100: y=64; 3'b101: y=125; end case default: y=0; 3. Write the equivalent structural verilog code for the behavioral verilog code below that does a y=x function. input [2:0] x; output [6:0] y; reg [6:0] y; wire [2:0] x; always @(x) begin y=0; case(x) 3'b000: y=0; 3'b001: y=1; 3'b010: y=8; 3'b011: y=27; end 3'b100: y=64; 3'b101: y=125; end case default: y=0;