3)Cache Memory. A Cache Controller coordinates processor memory accesses A 128-bit wide data bus allows 16 bytes to be transferred in a one access cycle 128-bit data bus Cache Memory Main Memory Processor Cache Controller 5 nanoseconds System Clock Period Memory Organization: 24 bytes Main Memory Size Cache Data Memory Size Cache Line Size 12 2 bytes 64 bytes (512-bits) Cache Policies: Write Hit Write Miss Main Memory Timing: Write-Back Write-NO Allocate Delay Time to Output Data from Memory Hold Time to Store Data in Memory 12 cycles 8 cycles Cache Memory Timing: Delay Time to Output Data from Cache Hold Time to Store Data in Cache 2 cycles 1 cycles Memory Access Statistics: Probability that an access is a READ Probability that a READ access is a HIT Probability that a WRITE access is a HIT Probability that Replacement Line is DIRTY 80% 60% 60% | 50% Indicate which bits of a main memory address are the tag field, index field and offset field when the cache organization is a) Direct Mapped b) Fully Associative 24-bit c) 16-Way Set Associative 24-bit