You are building a system around a processor with in order execution that runs at $1\mathrm{.}1$ GHz and has a CPI of $0\mathrm{.}7$ excluding memory accesses. The only instructions that read or write data from memory are loads Exercises by Amr Zaky $$ B$-63(20\%$ of all instructions$)$ and stores $(5\%$ of all instructions$).$ The memory sys tem for this computer is composed of a split L$1$ cache that imposes no penalty on hits. Both the I$-$cache and D$-$cache are direct mapped and hold $32$ KB each. The I$-$cache has a $2\%$ miss rate and $32-$byte blocks, and the D$-$cache is write through with a $5\%$ miss rate and $16-$byte blocks. There is a write buffer on the D$-$cache that eliminates stalls for $95\%$ of all writes. The $512$ KB write$-$back, unified L$2$ cache has $64-$byte blocks and an access time of $15$ ns$.$ It is connected to the L$1$ cache by a $128-$bit data bus that runs at $266$ MHz and can transfer one $128-$bit word per bus cycle. Of all memory references sent to the L$2$ cache in this system, $80\%$ are satisfied without going to main memory. Also, $50\%$ of all blocks replaced are dirty. The $128-$bit$-$wide main memory has an access latency of $60$ ns$,$ after which any number of bus words may be transferred at the rate of one per cycle on the $128-$bit$-$wide $133$ MHz main memory bus. a$.[10]$ What is the average memory access time for instruction accesses? b$.[10]$ What is the average memory access time for data reads? c$.[10]$ What is the average memory access time for data writes? d$.[10]$ What is the overall CPI, including memory accesses?