4 (Based on COD 5.7) This exercise examines the impact of different cache designs, specifically comparing associative caches to the direct-mapped caches. For these exercises, refer to the address stream shown in Exercise 2 12, 720, 172, 8, 764, 352, 760, 56, 724, 176, 744, 1012 4.1 Using the sequence of references from Exercise 2, show the final cache contents for a three-way set associative cache with two-word blocks and a total size of 24 words. Use LRU replacement. For each reference identify the index bits, the tag bits, the block offset bits, and if it is a hit or a miss. 4.2 Using the references from Exercise 2, show the final cache contents for a fully associative cache with one-word blocks and a total size of 8 words. Use LRU replacement. For each reference identify the index bits, the tag bits, and if it is a hit or a miss. 4.3 [15] Using the references from Exercise 2, what is the miss rate for a fully associative cache with two-word blocks and a total size of 8 words, using LRU replacement? What is the miss rate using MRU (most recently used) replacement? Finally, what is the best possible miss rate for this cache, given any replacement policy? 4 (Based on COD 5.7) This exercise examines the impact of different cache designs, specifically comparing associative caches to the direct-mapped caches. For these exercises, refer to the address stream shown in Exercise 2 12, 720, 172, 8, 764, 352, 760, 56, 724, 176, 744, 1012 4.1 Using the sequence of references from Exercise 2, show the final cache contents for a three-way set associative cache with two-word blocks and a total size of 24 words. Use LRU replacement. For each reference identify the index bits, the tag bits, the block offset bits, and if it is a hit or a miss. 4.2 Using the references from Exercise 2, show the final cache contents for a fully associative cache with one-word blocks and a total size of 8 words. Use LRU replacement. For each reference identify the index bits, the tag bits, and if it is a hit or a miss. 4.3 [15] Using the references from Exercise 2, what is the miss rate for a fully associative cache with two-word blocks and a total size of 8 words, using LRU replacement? What is the miss rate using MRU (most recently used) replacement? Finally, what is the best possible miss rate for this cache, given any replacement policy