4. Complete VHDL code for the block diagram below. [10 A2 B2 A1 B1 A0 B0 A B A B entity addsub is Port ( A : in STD,LOGIC-VECTOR (3 downto 0); B:in STD-LOGIC-VECTOR (3 downto 0) Subtraction: in STD_LOGIC; s:out STD-LOGCVECTOR (3 downto end addsub architecture Behavioral of addsub is COMPONENT FulAdder is Port (A: in STD_LOGIC B: in STD LOGIC; Cin: in STD LOGIC Sum: out STD LOGIC Co: out STD LOGIC) end component begin