$4.$ In this problem we examine how pipelining affects the clock cycle time of the processor. Problems inthis exercise assume that individual stages of the datapath have the following latencies.IF ID EX MEM WB$250$ ps $400$ ps $250$ ps $300$ ps $200$ psAlso, assume that instructions executed by this processor are broken down as follows. $[$Total $20$ pts$]$ALU$/$logic Jump$/$Branch Load Store$45\%20\%20\%15\%($a$)$ What is the clock cycle time in a pipelined and non$-$pipelined processor? $[4]($b$)$ What is the total la