$4-$ Suppose the base CPI with a perfect memory system is $1\mathrm{.}5,$ i$.$e$.,CP{U}_{\text{e}\text{x}\text{e}\text{c}}=1\mathrm{.}5.$ Determine which cache

configuration is the best by computing the CPU time for the three caches below:

$($a$)16-$Kbyte direct$-$mapped unified cache using write$-$back and has a miss rate of $0\mathrm{.}029.$

$($b$)16-$Kbyte $2-$way, set$-$associative unified cache using write$-$back and has a miss rate of $0\mathrm{.}022.$

$($c$)32-$Kbyte direct mapped unified cache using write$-$back and has a miss rate of $0\mathrm{.}02.$

Assume the following:

The memory system has a unified cache $($for instruction and data$)$ and main memory $($there is no L$2$ cache$).$

Main memory latency is $40$ clock cycles, the bandwidth between main memory and cache is $64$ bits per clock

cycle and that $50\%$ of the blocks in the cache are dirty.

There are $64$ bytes per block and $20\%$ of the instructions are load and store operations.

There is no write buffer.

$CC{T}_{16K,2-\text{w}\text{a}\text{y}}=1\mathrm{.}32CC{T}_{16K,1-\text{w}\text{a}\text{y}}$

$CC{T}_{32K,1-\text{w}\text{a}\text{y}}=1\mathrm{.}09CC{T}_{16K,1-\text{w}\text{a}\text{y}}$