$($b$)$ Calculate the performance of a processor taking into account stalls due to data cache and instruction cache misses. The data cache $($for loads and stores$)$ is the same as described above and $30\%$ of instructions are loads and stores. The instruction cache has a hit rate of $90\%$ with a miss penalty of $50$ cycles. Assume the base CPI using a perfect memory system is $1\mathrm{.}0.$ Calculate the CPI of the pipeline, assuming everything else is working perfectly. Assume the load never stalls a dependent instruction and assume the processor must wait for stores to finish when they miss the cache. Finally, assume that instruction cache misses and data cache misses never occur at the same time. $($b$\mathrm{.}1)$ Calculate the additional CPI due to the icache stalls. $(2$ pts$)($b$\mathrm{.}2)$ Calculate the additional CPI due to the dcache stalls. $(2$ pts$)($b$\mathrm{.}3)$ Calculate the overall CPI for the machine. $(2$ pts$)$