4.13 This exercise is intended to help you understand the rela- tionship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequence of instructions, and assume that it is executed on a 5-stage pipelined datapath: add r5, r2, r1 lw r3, 4(r5) lw r2, 0(r2) or r3, r5, r3 sw r3, 0(r5) 4.13.1 [5] If there is no forwarding or hazard detec- tion, insert nops to ensure correct execution. 4.13.2 [10] Repeat 4.13.1 but now use nops only when a hazard cannot be avoided by changing or rearranging these instructions. You can assume register R7 can be used to hold temporary values in your modified code. 4.13.3 [10] If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when this code executes? 4.13.4 [20] If there is forwarding, for the first five cycles during the execution of this code, specify which sig- nals are asserted in each cycle by hazard detection and for- warding units in Figure 4.60. 4.13.5 [10] If there is no forwarding, what new inputs and output signals do we need for the hazard detection unit in Figure 4.60? Using this instruction sequence as an exam- ple, explain why each signal is needed. 4.13.6 [20] For the new hazard detection unit from part e, specify which output signals it asserts in each of the first five cycles during the execution of this code. ID/EX MemRead Hazard detection unit ID/EX FDW WE EX/MEM Control X2 MEMWB IFND WB Ex- Registers Instruction Instruction memory 3X Data memory X IF ID Registers IFAD RegisterRI IFAD. Registert IF ID. Register Rd ID EX Register Esx Forwarding unt FIGURE 4.60 Pipelined control overview, showing the two multi- plexors for forwarding, the hazard detection unit, and the forwarding unit. Although the ID and EX stages have been simplifiedthe sign- extended immediate and branch logic are missingthis drawing gives the essence of the forwarding hardware requirements