4.16 In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250ps 350ps 150 ps 300ps 200ps Also, assume that instructions executed by the processor are broken down as follows ALU/Logic 45% Jump/Branch Load Store 20% 20% 15% 4.16.1 (5] What is the total latency of an I d instruction in a pipelined and non-pipelined processor