4.2 The basic single-cycle MIPS implementation in Figure 4.2 can only implement some instructions. New instructions can be added to an existing Instruction Set Architecture (ISA), but the decision whether or not to do that depends, among other things, on the cost and complexity the proposed addition introduces into the processor datapath and control. The first three problems in this exercise refer to the new instruction:

Instruction: LWI Rt,Rd(Rs) Interpretation: Reg[Rt] = Mem[Reg[Rd]+Reg[Rs]]

4.2.1 [10] Which existing blocks (if any) can be used for this instruction?

4.2.2 [10] Which new functional blocks (if any) do we need for this instruction?

4.2.3 [10] What new signals do we need (if any) from the control unit to support this instruction?

CLK CLK WE PC PC 0 Ad RD nstr Data Memory WD mem datapath control CLK PC Write Branch or D Control PCSrc10 Unit ALUControl 30 Mem Write ALUSrcB1 RWrite 31:28 op ALUSrCA. RegWrite 5:0 Funct CLK CLK WE3 25:2 A1 RD nstr RD2 EN 20:16 A3 CLK Register File Data WD3 5:0 Sign Extend 25.0 Gump) CLK 31:28 mmExt