5. Below are some assumptions of memory access times: 1 memory bus clock cycle to send...

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5. Below are some assumptions of memory access times: 1 memory bus clock cycle to send the address 10 memory bus clock cycles for each DRAM access initiated 1 memory bus clock cycle to send a word of data Based on these assumptions, please calculate the miss penalty of a four-word block for the following organizations of memory. (10%) (1) One-word-wide memory organization: the memory and the bus between the processor and the memory are both one word wide. (3%) (2) Wider memory organization: the memory and the bus between the processor and the memory are widened to two words. (3%) (3) Interleaved memory organization: the memory chips are organized in four banks, where each bank is one word wide, without widening the interconnection bus (in other words, the bus is still one word wide). (4%) 5. Below are some assumptions of memory access times: 1 memory bus clock cycle to send the address 10 memory bus clock cycles for each DRAM access initiated 1 memory bus clock cycle to send a word of data Based on these assumptions, please calculate the miss penalty of a four-word block for the following organizations of memory. (10%) (1) One-word-wide memory organization: the memory and the bus between the processor and the memory are both one word wide. (3%) (2) Wider memory organization: the memory and the bus between the processor and the memory are widened to two words. (3%) (3) Interleaved memory organization: the memory chips are organized in four banks, where each bank is one word wide, without widening the interconnection bus (in other words, the bus is still one word wide). (4%)