Question: 5. Design a synchronous sequential circuit represented by the following state diagram using explicit style Verilog code. Assume a positive-edge clock. Also assume that

5. Design a synchronous sequential circuit represented by the following state diagram

5. Design a synchronous sequential circuit represented by the following state diagram using explicit style Verilog code. Assume a positive-edge clock. Also assume that reset will be done when the reset signal will go from 1 to 0. reset 1/10 A 0/01 1/01 D B 1/11 0/10 0/10 0/10 E 0/10 1/00 1/11

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