5.3 How many address bits are required to access all addresses of 128M x 16 memory? The required address bits is 27. [2] 5.4 How many of these lines are connected to the address inputs of all chips? 5.5 How many of adress lines must be decoded for the chip select inputs? 5.6 Specify the size of the decoder. 5.7 How many data in/out bits constitute the data bus? 5.8 How many chips of 32M x 8 are required to provide a memory of 128M x 16? 8 Data chips are required. [2] 5.9 Is this design of wider or longer memory? 5.10 What are the capacity and width of 128M x 16 memory? The capacity is 8 million of locations, the width is 16 bits. [2] [2] [2] [2] [2] [2] 5.3 How many address bits are required to access all addresses of 128M x 16 memory? The required address bits is 27. [2] 5.4 How many of these lines are connected to the address inputs of all chips? 5.5 How many of adress lines must be decoded for the chip select inputs? 5.6 Specify the size of the decoder. 5.7 How many data in/out bits constitute the data bus? 5.8 How many chips of 32M x 8 are required to provide a memory of 128M x 16? 8 Data chips are required. [2] 5.9 Is this design of wider or longer memory? 5.10 What are the capacity and width of 128M x 16 memory? The capacity is 8 million of locations, the width is 16 bits. [2] [2] [2] [2] [2] [2]