5.5 For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache Tag 63-10 Index Offset 9-5 4-0 5.5.1 [5] What is the cache block size (in words)? 5.5.2 [5] How many blocks does the cache have? 5.5.3 [5] What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded. Addre ss Hex 00 041084E8AO 400 1E 8CC1CB4 884 Dec 0 4 16 132 232 160 1024 30140 31001802180 5.5.4 [20] For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any) 5.5.5 [5] What is the hit ratio? 5.5.6 [5] List the final state of the cache, with each valid entry represented as a record of . For example, 5.5 For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache Tag 63-10 Index Offset 9-5 4-0 5.5.1 [5] What is the cache block size (in words)? 5.5.2 [5] How many blocks does the cache have? 5.5.3 [5] What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded. Addre ss Hex 00 041084E8AO 400 1E 8CC1CB4 884 Dec 0 4 16 132 232 160 1024 30140 31001802180 5.5.4 [20] For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any) 5.5.5 [5] What is the hit ratio? 5.5.6 [5] List the final state of the cache, with each valid entry represented as a record of . For example