5.5 For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache 5.5.1 15] $5.3> What is the cache block size (in words)? 5.5.2 15] $5.3> How many blocks does the cache have? 5.5.3 [5] What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded. 5.5.4 [20] 5.3> For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any). 5.5.5 [5] What is the hit ratio? 5.5.6 I5l 85.3> List the final state of the cache, with each valid entry represented as a record of index, tag, data>. For example