6. (1-bit Comparator Module) In class, we have discussed the modified 1-bit comparator module which can be used as a building block for multi-bit arithmetic comparators. The inputs of the module are the data input bits a and y, and the control input bits Gin, Ein and Li (these three bits indicate the status of the magnitude of the n-bit binary numbers X and Y in the bit positions to the left of current bit). The outputs of the module are the status output bits G , E , and Lout (these three bits indicate the status of the magnitude of the binary nmbers X and Y in the bit positions to the left of the current bit and including the current bit) (a) Write down the truth table for the 1-bit comparator module. (b) Write Verilog code to implement the 1-bit comparator module