$6.(30$pts$)$ For the following circuit, Flip$-$Flops have a Clock$-$to$-$Q propagation delay of $70$ ps$,$ a Clock$-$to$-$Q contamination delay of $50$ ps $,$ a set$-$up time of $60$ ps $,$ and a hold time of $20$ ps $.$ An OR gate has a propagation delay of $100$ ps and a contamination delay of $55$ ps$.$

$($a$)$ Determine the maximum clock frequency assuming there is no clock skew.

$($b$)$ How much clock skew can this circuit tolerate if it must operate $2$ GHz $?$

$($c$)$ How much clock skew can this circuit tolerate before the race happens?