6) Consider a cell-based 8-bit 8-bit Cary-save array multiplier.

VHDL code WITHOUT using SLL or SRL or any Shift Operator classes.

a. Draw the architecture schematic of the RTL. b. Estimate how many AND gates and Full adders it requires (Assume half adders are implemented by full adders). c. What is the critical-path delay of this multiplier, assuming an AND gate delay is tA, and adder delay is tAdd