$9\mathrm{.}15$ Advanced Optimization

Lab Description:

Drive the anodes of two digits for a seven segment display. The digits should display all hex Values $0$x$00$ to OxFF. You must use module instantiation. $($Read Below$)$ Assume the segments are active high. Always drive the decimal point $($DP$)$ anode low $($off$).$ See the diagram given in file download for context.

Input Signals:

Value $-8$ bits Value$[7]$ to Value$[4]$ drive the $10$s place digit. Value$[3]$ to Value$[0]$ drive the $1$s place digit.

Output Signals:

SevenSegDig$1-8$ bits, $1$s place output. SevenSegDig$2-8$ bits, $10$s place output.

The MSB of the outputs should be the DP value, then F value... the LSB of the output should be the A value.

Use anodes B$,$C to display $1$

Use anodes A$,$C$,$D$,$E$,$F$,$G to display $6$

Use anodes A$,$B$,$C$,$D$,$F$,$G to display $9$

Use anodes C$,$D$,$E$,$F$,$G to display B

Use anodes A$,$D$,$E$,$F to display $C$

Use anodes B$,$C$,$D$,$E$,$G to display D

Reference Zybook sections: $2\mathrm{.}13-2\mathrm{.}14$

Useful Syntax:

Module Instantiation: Verilog modules can be called within other modules by creating new module instances. This is useful for creating more complex designs and maintaining organization.