$9.($a$)$ Draw a state diagram and write a behavioural Verilog code of a Mealy

synchronous state machine having a single input, x$\_$in$,$ and a single output

y$\_$out, such that y$\_$out is asserted if the total number of $1\text{'}$s received is a

multiple of $3.$

OR

$9.($b$)$ Design a Moore FSM using T$-$FFs which has a single input, x $\_$in$,$ and a single

output y$\_$out, such that y$\_$out is asserted if the total number of $0\text{'}$s received is

a multiple of $3.$ Write a behavioural Verilog code.