$[9$ points$]$ Given a CPU that runs at $2$GHz clock frequency and has a base CPI of $1($without considering load and store instructions that access the memory$).$ It has a L$1$ cache whose access time is $0\mathrm{.}5$ns and a L$2$ cache whose access time is $5$ns$.$ The DRAM access latency is $50$ns$.$ Assume $10\%$ of the instructions in a program are memory access instructions $($i$.$e$.,$ load and store instructions$).$ On average, for all the L$1$ cache access, it has a hit ratio of $80\%$; for all the L$2$ cache access, it has a hit ratio of $95\%.$

a$)[3$ points$]$ How many CPU clock cycles does it take to access L$1$ cache, L$2$ cache, and DRAM, respectively?

b$)[2$ points$]$ What's the global percentage of instructions $($i$.$e$.,$ the percentage among all instructions$)$ that will have a L$1$ miss and L$2$ miss, respectively?

c$)[2$ points$]$ What's the average memory access time $($AMAT$)?$ Note: detailed computation steps must be included; otherwise, you will lose $1$ point.

d$)[2$ points$]$ What's effective CPI for this program? Note: detailed computation steps must be included; otherwise, you will lose $1$ point.