A cache holds 64 words where each word is 4 bytes. Assuming a 32-bit address, give a. A direct-mapped cache with block size = 8 words b. 2-way set-associative cache with block size = 8 words c. 4-way set-associative cache with block size = 4 words d. A fully associative cache with block size =16 words. Complete the table for each cache. Here is a series of addresses in hexadecimal: 20, 4C, 14, 18, 23, 09, 28, 60, 10, 17 Assume a LRU replacement algorithm. For the four caches in problem 1, draw each cache as it would appear at the end of the series of references. Include the valid bit, dirty bit, and tag. Note that these are addresses, not block numbers. Show the memory contents with the range of byte addresses such as M[20-23] for the address 22 (if the block size is 1 word)