A certain Processor has the following relevant specs: Clock cycle: 1 time unit Pipelined: yes Pipeline Stages: 6, assume all stages are of equal duration, and that each stage takes 1 Clock cycle Stage actions: FI, DI, CO, FO, EI, WO (see textbook page 446 for descriptions)

Memory access: SINGLE PORT, thus only one memory access operation can occur per clock cycle Instructions: assume ALL instructions go through ALL stages, stalling (causing a pipeline bubble) if necessary Registers: N/A Cache: N/A

Bus: N/A ______________________________________________________________________________________

Given the following program segment written in (a certain) Assembly language: (operands are 1st and 2nd vars, the result is stored in the 3rd var...C=A and B) AND A, B, C OR D, E, F

AND G, H, I

OR J, K, L

AND M, N, O

OR P, Q, R

considering hazards...

Repeat for the following program segment and again considering hazards:

NAND A, B, C

OR D, E, F

NOR E, F, G

XOR H, I, G

AND I, J, K N

AND K, L, K

Fetch instruction (FI): Read the next expected instruction into a buffer. Decode instruction (DI): Determine the opcode and the operand specifiers. Calculate operands (CO): Calculate the effective address of each source operand. This may involve displacement, register indirect, indirect, or other forms of address calculation. Fetch operands (FO): Fetch each operand from memory. Operands in regis- ters need not be fetched. Execute instruction (EI): Perform the indicated operation and store the result, if any, in the specified destination operand location. Write operand (WO): Store the result in memory