a$)$ Design a completely labeled $4-$bit serial$-$in$/$parallel out shift register using negative edge triggered D flip$-$flop$($s$).$ The shift operation occurs on the positive edge of the clock input CP$.$ The $\backslash (\backslash$overline$\{$M R$\}\backslash )$ input provides asynchronous resetting of all flip$-$flops.

b$)$ Construct a $4-$bit Johnson counter. List the used and unused states of the counter. Determine the next state for each of these states, and show that if the counter finds itself in an invalid state, it does not recover to a valid state. Draw the state diagram.