A direct mapped cache on a system with 64-bit addresses i s accessed with the address divided i nto 5 bits of offset, 5 bits of i ndex, and 54 bits of tag. 1. What is the cache block size (in words)? 2. How many blocks (lines) does the cache have? 3. If this cache only saves tag and valid bits in addition to data in the cache, what is the ratio of total bits required to implement this cache over the data size of the cache