STEPS PLZ

Consider a computer system with $8-$bit memory addresses, a cache with $4$ blocks and the size of each block $2$ bytes.

$\backslash$table$[[$Address$,$Data$],[00101010,0$x$12$F$0],[00101011,0$xFFC$0],[11001100,0$x$0001],[11001010,0$x$96$AA$],[11001011,0$x$81$CD$],[00111101,0$x$010$E$],[00111100,0$x$557$C$],[00101100,0$x$1234]]$

A$.$ Assume a direct mapped cache is used, answer the following quesitons:

a$.$ How many data bytes can be stored in the cache? Exclude the tag and valid bit.

b$.$ How many bits are used for the tag? How many bits are used for the block index? How many bits are used for the offset?

c$.$ Given the following addresses, show the tag and offset bits for each addresses: $11001010$ and $0010010.$

d$.$ Consider the following sequence of cache read operations to the following addresses: $00101010,00101011,11001100,11001010,11001011,00111101,00111100,00101100.$

Use the following table to show the sequence of tags accessed in each tag block starting at the top.

$\backslash$table$[[$Block$,$Tag,Data$],[0,,],[,],[1,,],[,],[,],[,],[2,,],[,],[,],[,],[3,,],[,],[,],[,]]$