A non$-$uniform memory access $($NUMA$)$ multiprocessor machine has $4$ processors, each with $100,000,000$ bytes of memory, organized as follows: processor n has the memory locations from $($n$-1)*100,000,000$ to n$*(100,000,000)-1.$ For example, processor $4$ has the memory location $[300,000,000..\mathrm{.}399,999,999].$ The system implements a directory$-$based cache coherency protocol. The caches are direct mapped, block size is $1000$ and the number of blocks in each cache is $1000.$ Trace the evolution of the states of the caches, directory, memory locations and messages for the following sequence of events:

$1)$ Processor $1$ reads location $200,050,003$

$2)$ Processor $2$ reads location $200,050,004$

$3)$ Processor $3$ reads location $200,050,004$

$4)$ Processor $1$ reads location $200,050,004$

$5)$ Processor $3$ writes location $200,050,002$

$6)$ Processor $3$ writes location $300,050,002$