A process has a sequential periodic address access pattern as follows: Page1, Page2, Page3,..., Page100, Page1, Page2, Page3, ..., Page100, Page1, Page2, ... and so on. Assume that the RAM can accommodate at most 50 pages and TLB can store at most 10 entries. Also, it is known that if the page replacement policy is LRU or FIFO, then the process performance suffers due to the high number of page faults.

Now, consider the case where the TLB replacement policy mirrors the page replacement policy. For instance, if the page replacement is LRU then the TLB replacement policy is also LRU (and similarly for FIFO). Given this scenario, does the process performance become worse due to the identical TLB entry replacement policy? If Yes, why? If No, why?