Question: A processor has a cache, with 12-word blocks. The processor miss rates are as follows: Instruction miss rate of 4% Data miss rate of 6%

A processor has a cache, with 12-word blocks. The processor miss rates are as follows: Instruction miss rate of 4% Data miss rate of 6%

70% of the instructions contain a data reference, which could cause a data miss. If the cache miss penalty is (8+ block size) cycles, what is the total number of miss cycles per instruction for this machine (to TWO decimal places)?

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