A processor$$s core has an on$-$chip L$1$ cache and an off$-$chip L$2$ cache. These are backed up by

DRAM. The L$1$ cache has a hit time of $\mathrm{.}25$ ns and a hit rate of $88\mathrm{.}7\%,$ the L$2$ cache has a hit

time of $1\mathrm{.}5$ ns and a hit rate of $94\mathrm{.}2\%,$ and DRAM has an access time of $20$ ns and a $100\%$ hit

rate.

a$.$ What is the effective access time for this processor?

b$.$ We add a second on$-$chip cache $($a new L$2)$ making the existing L$2$ into an L$3$ cache. The

new L$2$ has a hit time of $\mathrm{.}8$ ns and a hit rate of $91\mathrm{.}9\%.$ What is the effective access time

now?