a Q2 [12 points] Single-Cycle Processor Consider the single-cycle datapath and control shown below for a MIPS-like processor. It can implement only some instructions: Branch Target Address Jump Target=PC[31:28) II Imm26 Extop Next PC Address Imm16 Ext +1 ALU result Zero Rs /* Instruction Memory Address Instruction RA BUSA Registers RB BusB RW Bus 1 Rt Data Memory Address Data_out Data_in Rd PCS clk func ALUop MemRd WBdata RegDst RegWr Op PC Ctrl ALU Ctrl Memwr ExtOp ALUSrc Zero Main Control a) (6 points) Consider the execution of: OR Rd, Rs, Rt Fill-in the control signal values for the OR instruction in the table shown below. Which blocks are not used by this instruction? (Even if they produce output) Instruction RegDst RegWr ALUSC MemRd Mem Wr WBdata PCSrc OR Rd, Rs, Rt b) (6 points) Consider the execution of: SWRt, Imm(Rs) Fill-in the control signal values for the SW instruction in the table shown below. Which blocks are not used by this instruction? (Even when they produce output) Instruction RegDst RegW1 ALUSC MemRd MemWr WBdata PCSrc SW Rt, Imm(Rs) 1