Question: A single - cycle processor takes 1 0 0 ns per instruction. It is perfectly pipelined into 1 0 stages with pipeline register that take

A single-cycle processor takes 100ns per instruction. It is perfectly pipelined into 10 stages with pipeline register that take 2ns. What change in instruction latency can you expect compared to the single-cycle processor?
A.10% speedup
B.20% speedup
C. Same latency as single-cycle processor
D.20% slowdown

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