A snooping cache coherence protocol is implemented such as the one discussed in class, in a symmetric shared-memory multiprocessor with 3 processors sharing a bus, Describe the steps of the coherence protocol mentioning the eventual state of the data block in the caches of each of the 3 processors for each of the instructions below. Note that the caches are direct-mapped and that each cache block only stores one word and words X and Y map to the same cache block in each cache (i.e. X and Y can’t be both in the cache at the same time). Assume that at the beginning X and Y are not in any of the caches.

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1 Processor 1 P1 writes to X P1 sends a write request to the bus Other processors P2 and P3 snoop on ... View the full answer