A synchronous Moore FSM has a single input, x_in , and a single output y_out . The
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A synchronous Moore FSM has a single input, x_in , and a single output y_out . The machine is to monitor the input and remain in its initial state until a second sample of x_in is detected to be 1. Upon detecting the second assertion of x_iny_out is to asserted and remain asserted until a fourth assertion of x_in is detected. When the fourth assertion of x_in is detected the machine is to return to its initial state and resume monitoring of x_in .
(a) Draw the state diagram of the machine.
(b) Write and verify a Verilog model of the machine.
Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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